Materials Transactions Online

Materials Transactions, Vol.52 No.01 (2011) pp.118-123
© 2011 The Japan Institute of Metals

Effect of Annealing Ambient on Structural and Electrical Properties of Ge Metal-Oxide-Semiconductor Capacitors with Pt Gate Electrode and HfO2 Gate Dielectric

S. V. Jagadeesh Chandra1, Myung-Il Jeong1, Yun-Chang Park2, Jong-Won Yoon3 and Chel-Jong Choi1,4

1School of Semiconductor and Chemical Engineering, Semiconductor Physics Research Center (SPRC), Chonbuk National University, Jeonju 561-756, Korea
2Measurement and Analysis Division, National Nanofab Center (NNFC), Daejeon 305-343, Korea
3Department of Advanced Materials Science and Engineering, Dankook University, Cheongan 330-714, Korea
4Department of BIN Fusion Technology, Chonbuk National University, Jeonju 561-756, Korea

We fabricated Ge metal-oxide-semiconductor (MOS) devices with Pt/HfO2 gate stacks and investigated the effect of thermal treatment on their structural and electrical properties in oxygen (O2) and forming gas (FG) environments. The annealing ambient dependency of the structural and electrical properties of Ge MOS devices was directly compared to that of Si MOS devices. For both Ge and Si MOS devices, the thermal treatment process led to a decrease in accumulation capacitance regardless of the annealing ambient. The interfacial layer (IL) at the HfO2/Ge stack was much thinner than the HfO2/Si stack. O2 annealing resulted in the improvement of the HfO2 interfacial quality of Ge and Si MOS devices, although the improvement of the Ge devices was greater than that of the Si devices. FG annealing was much more effective in the reduction of interface state density (Dit) in Si devices than in Ge devices. A negligible IL at a HfO2/Ge stack could be a main cause of degraded electrical performance of a Ge device with FG annealing.

(Received 2010/9/16; Accepted 2010/10/22; Published 2010/12/8)

Keywords: metal-oxide-semiconductor (MOS), germanium, silicon, HfO2, annealing, interfacial layer, density of interface state

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