Materials Transactions, Vol.47 No.05 (2006) pp.1417-1419
© 2006 The Japan Institute of Metals
Filling a Narrow and High Aspect-Ratio Trench with Electro-Cu Plating
Yasunori Chonan1, Takao Komiyama1, Jin Onuki2, Takahiro Nagano3, Haruo Akahoshi4, Takeyuki Itabashi5, Tatuyuki Saito6 and Khyoupin Khoo2
1Department of Electronics and Information Systems, Factory of System Science and Technology, Akita Prefectual University, Yurihonjyo 015-0055, Japan
2Department of Materials Science and Engineering Ibaraki University, Hitachi 316-8511, Japan
3Intellexres Laboratory, Hitachi 316-0015, Japan
4Hitachi Research Laboratory, Hitachi 319-1292, Japan
5Advanced Research Laboratory, Hitachi Ltd., Hatoyama 350-0395, Japan
6Hitachi, Ltd., Hitachi Device Development Center 198-8512, Japan
Copper electroplating has been used for making interconnections in large-scale integration (LSI). Sub-100-nm-wide, deep trenches with aspect-ratios over 6 were fully filled by optimizing DC and pulse electroplating processes. Grain sizes of Cu of sub-100-nm wide trenches after electroplating were 70 nm for DC electroplating and 58 nm for pulse electroplating. The Cu grain sizes of Cu interconnects by DC plating after electroplating increased with the annealing temperature.
(Received 2006/1/27; Accepted 2006/3/27; Published 2006/5/15)
Keywords: copper, electroplating, semiconductor, annealing
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